Vegemite
Wouldn't you know a Vegemite jar would be the perfect size as a jig for this thing?
Anyway, from what I can discern, it seems as though the timing is equal for each coil. I think once someone can fire off a UCC27321P driver chip we'll have a better idea about pulse width. I think it will be as W said in the video:
" ... note that the pulses are a little further apart but notice how small they are so that the duty cycle has come down from somewhere about, I think it was about eight or ten percent, down to around zero point three percent."
This is very 'key' info'! as well as:
" ... now when we do our power generation, we do not need to do that. All we need is we need a very fast rising field and a very fast collapsing field, and we need to have as many of them as humanly possible and obviously without saturating our core ...".
If someone has some insight into what frequency W pulsed at, that would be valuable to the effort. The 3 frequencies for the 'cell' application are well known, but I'm not sure if they are approaching saturation in those applications. According to the video showing the gate signal scope shots, I think I can see that the time scale is set to 50usec/division ... does anyone else see it differently?
Anyway I'm building the new comparator now, will test, and maybe hook up a UCC27321P driver chip and see if I can fire my IRF540Z's without frying either FET or Chip.
Oh and:
This wasn't aimed at anyone in particular. Sorry if it sounded that way.
Later
Originally posted by Farmhand
View Post
Anyway, from what I can discern, it seems as though the timing is equal for each coil. I think once someone can fire off a UCC27321P driver chip we'll have a better idea about pulse width. I think it will be as W said in the video:
" ... note that the pulses are a little further apart but notice how small they are so that the duty cycle has come down from somewhere about, I think it was about eight or ten percent, down to around zero point three percent."
This is very 'key' info'! as well as:
" ... now when we do our power generation, we do not need to do that. All we need is we need a very fast rising field and a very fast collapsing field, and we need to have as many of them as humanly possible and obviously without saturating our core ...".
If someone has some insight into what frequency W pulsed at, that would be valuable to the effort. The 3 frequencies for the 'cell' application are well known, but I'm not sure if they are approaching saturation in those applications. According to the video showing the gate signal scope shots, I think I can see that the time scale is set to 50usec/division ... does anyone else see it differently?
Anyway I'm building the new comparator now, will test, and maybe hook up a UCC27321P driver chip and see if I can fire my IRF540Z's without frying either FET or Chip.
Oh and:
Hi all
Originally Posted by gmeast View Post
... they would inject "you need to be around 0.3% Duty Cycle and around 2.5usec pulse width" ... and off the cuff advice like that.
I am not competent to offer any advice, but I feel that he,who first posted about "0.3% Duty Cycle" may have made a mistake of the kind of a typing error.
He may have meant to say:
"approx. 30% ON-time per cycle"
which is the same as 0.3
which would again be the same as saying "approx. two thirds OFF-time per cycle".
Again: I think it could have been a simple communications error (but that just is some gut feeling of mine and I may be wrong).
Originally Posted by gmeast View Post
... they would inject "you need to be around 0.3% Duty Cycle and around 2.5usec pulse width" ... and off the cuff advice like that.
I am not competent to offer any advice, but I feel that he,who first posted about "0.3% Duty Cycle" may have made a mistake of the kind of a typing error.
He may have meant to say:
"approx. 30% ON-time per cycle"
which is the same as 0.3
which would again be the same as saying "approx. two thirds OFF-time per cycle".
Again: I think it could have been a simple communications error (but that just is some gut feeling of mine and I may be wrong).
Later
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