Originally posted by Cornboy 555
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The cap shall be connected between driver output and GND. The cap is kind of simulation for FET in order to get rid for now of other phenomenons added by FETs themselves.
..........FET circuit ....................test circuit
- driver output-------------->driver output
- gate pin of FET------------>leg of cap
- inherent gate cap---------->test cap itself
- source pin of FET---------->leg of cap
- GND----------------------->GND
We expect a graph like this:
I suggest to test with cap because we can have differnt values and are able to get damn short leads (5mm if possible).
You connect your scope to driver output and GND.
Vote this behaviour here as a microscopic view (time wise) to cap behaviour compared to normal charging desicharging caps at DC and mainsAC conditions. You can still apply the vision of filling a bottle at a water tap and pooring the bottle later on. But here the cavity is very small like the cavity at a ink jet printer - filling and poorinig pico-litre of fluid (pico = 10^-12).
JS
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