Stanley Meyer Explained

[h20power]

Hi Radiant_Science,

Lets just agree to disagree on this one okay? For you want the Gas Processor to create the O3 and I want it to strip oxygen atoms of their electrons some four or more. Ozone is very bad as it eats up most types of seals. The GP is set up to not create O3 but lone O atoms these atoms are hit with electron collisions and photon bombardment in some of the absorption wavelengths of oxygen. Then this highly ionized air gas is mixed with the water mist that most of it will turn into vapor due to the phase diagram of water in that the water is about 85-90 degrees C under pressure and is injected into a low pressure zone.

As this mixture moves through the voltage zone the water molecules are charge each of the same polarity so they will repel each other and not form larger droplets, that overcomes the adhesive properties of water taking on the same charge. At around 20 kv the cohesive properties are overcome and the water droplet divides into two smaller droplets dividing the voltage between the two as it does, but as long as it is in the voltage zone it will be recharged and the process repeats until a critical volume is reached. Once at the critical volume and charged to the maximum degree again the molecule simply breaks down into it's component elements for this is an image charge with very little current not enough to ignite the mixture just to break it apart. Now why it is still in the voltage zone the voltage zone acts like the gas processor but only electrons are colliding with the freshly created oxygen and hydrogen atoms. When I ran my numbers on the speeds of the fuel injectors and the length of the voltage zone compared to a frequency of 50 kHz I got a total of 86-89 hits on the water molecules, already ionized air gases, and recirculated exhaust gases. So if it only take 40 hits to break down the water molecule into hydrogen and oxygen then the remaining hits will be on the hydrogen and oxygen atoms while still inside of the fuel injectors. Now raising the voltage will charge the water mist faster towards the dividing point.

As for the EEC on the injectors Meyer's only shows it as a amp consuming device inline with the positive side of the voltage zone. So that must be tested out to see just what it does.

The reason I wanted you to look at energy content calculations is if you did you would easily see that O3 + 6H does have more energy content than just plain 2H + O which is at 286 kJ/mol, but they both fall well short of gasolines 5088 kJ/mol (depending on grade). Only by stripping the oxygen atoms of 4 or more electrons will it surpass the energy content of gasoline. So if you don't allow the GP to strip these electrons off then you will not get the needed energy content to replace gasoline and if you allow the GP to produce O3 instead of striped oxygen atoms you will fall short on energy content. That is what I wanted you to see, the energy content in the reaction you are saying is taking place vs that of gasoline and then compare those numbers to what Meyer claims he was capable of doing. You will find that it wont match up to Meyer's claims.

You are right when you say it is unknown the chemical breakdown when the critical volume of water is reached: for is it H3O+(aq) + OH-(aq) = 4H (g) + 2O (g) or is it H2O(aq) = 2H (g) + O (g)? one of the two is happening, which one of the two as of now I can not answer. But yours seems more plausible due to the voltage stresses placed on the water molecules by the voltage zone.

Now what I think that quote you place on is saying is this; the unstable oxygen atoms have the necessary energy to reach in and take the hydrogen atoms from the water molecule if it comes into direct contact with the water molecules. I have run calculations showing that it does with a surplus of energy before on this thread.

Like I said before if you don't agree then lets just agree to disagree, okay? Thanks.


h2opower.

[h20power]

Just thought this was interesting to know: Graneau Paper on Water Explosions and others would like to read it too.

h2opower.

[h20power]

Just found something about water's spliting voltage it's called "Taylor Limit http://etd.caltech.edu/etd/available.../chapter_6.pdf. I was thinking someone must have looked at or found the voltage it takes to make a liquid divid with electric pressure and I found that site. Still learning how to apply the equation but it seem Taylor had already done this before.

Just asking and answering questions I might have on the Meyer technology to further my knowelge on the subject.


h2opower.

[handyandy]

Re:EEC

H2OPower,

I remembered seeing somewhere in Stan's writings that electrons were captured by hydrogen ions. I found it in this patent: U.S. 5149407 fig. 6D. If you follow the arrows some of the electrons are captured by hydrogen ions which would be a proton and 2 electrons H- which would probably be fairly stable until a spark ignition perhaps. A drawing doesn't actually mean that in reality that is what's happening but it gives an idea of what might be happening. Since there's 2 hydrogens to every oxygen that takes care of at least 2 oxygen electrons. The grid or whatever could then extract an additional 2 electrons for a higher ionization state for oxygen. The photon energy gives this potential an extra push in that direction given probabilities.

Regards,
Andy

[bussi04]

board layout complete and ready for download

Hello Stan Meyer tech experimentators ,

I have updated, expanded and corrected my recently published circuit in the appended layout.
before my routing takes place you should have a close look to the application contents and give feedback/corrections if necessary.
I have put most of SM functionality onto this board, also those parts we hadnīt discussed before. What I left out is accelerator pedal electronics and WFC pressure control electronics.

To give you a better overview I have made annotations for the original SM figures in the scheme.

Because of High Voltage I am concerned that the galvanic barrier between controller and driver circuit has to be obeyed. That means that no HV component can reside on the main pcb. So it gets a separate one.
Before routing I must take care for the fact that those paths dealing with high currents must be thicker than those for normal signal propagation.

Some resistor values I havenīt calculated up to now. If anyone has a good idea or backup information according to figure 5 values R19,20,21,22,23,25,26,32 this would be the right time to give me a hint .
The same for the voltage VEE at R23 in fig. 5. Any idea? I guess itīs identical with the driver/batt/supply voltage 12-24V, but Iīm not sure.

Some resistors get the value 0, that means that they are no real resistors but bridges for several purposes. circuit parts can be separated easily if a bridge is not installed. That may be necessary if later redesign should become necessary or new driver segments shall be integrated (i.e. R33).
Another case for bridge R2: as soon as we know the exact frequency produced from U3 then it may be necessary to change the value of RV1 and add a Resistor R2.

I donīt know if those fig. 12 parts (U9,U11,SW2,SW3,SW5,SW6) and fig. 7 parts (U12,U13,U14,SW7) are needed so you can implement them or leave them out.
IMPORTANT:
1. If you implement fig. 12 functionality bridge R11 MUST be left open.
2. U9 and U11 are SN74HCTxx circuits, that can only be supplied by +5V though they are CMOS . So if you add fig. 12 functionality you MAY NOT USE a 7808 but only 7805 as U1. I didnīt find a substitute in CD40xx. But thatīs no problem because the whole circuit will work with +5V. The only things that change are frequencies that can be adjusted with pots.

If one of you uses 8V and another one uses 5V and all other circuit values are the same those voltage dividers and RC-circuits will differ in behaviour and comparing results and support gets more difficult. So for practical reasons I would suggest to use 5V.

Thatīs for the moment, Iīll add the KiCad files as sm1.pdf (real sm1.zip) and 2 low res pictures of the schemes for those who have not yet installed KiCad . And ... clean up your glasses .
Be aware that zooming in with KiCad and implementing individual adds is a great benefit for learning KiCad.

The whole circuit remains beta until some experimentors have got first practical results and given feeback. I canīt do that alone!
capacitors and resistors may have to be changed so that timing gets optimized or as needed. so please donīt wait too long to take up your experiments otherwise the circuit canīt be finalized.

The next days Iīll upload the layout files. There is some work for me to do towards routing and footprints,

please give analytical feedback and
stay tuned,

greetings,
bussi04

Iīve finished Revision 0.2 of the Stan Meyer freedom circuit board.

The circuit has not been tested up yet, but I have corrected the detected errors of the very first version. Those high power circuit sections are realized with enhanced copper connection lines.

Iīll immediately give the layout to the manufacturer so that it will return back as a pcb in 10 days. Then Iīll add the circuits so that it boots up in lets say 15 days from now.
File sm2.pdf is a real sm2.zip (so please rename after download) and contains several files:
The named gerber-files are for the pcb manufacturer, sm1.sch is the KiCad scheme, sm2.net is the netlist and sm6_4.brd is the final board file.
freedom circuit rev. 0.2.pdf gives you a quick view at the board.

Iīll supply further informations to you as soon as I have assembled the board.
Please download now sm2.pdf and archive so that it`s spread …

greetings,
bussi04

[pmazz850]

Just found something about water's spliting voltage it's called "Taylor Limit http://etd.caltech.edu/etd/available.../chapter_6.pdf. I was thinking someone must have looked at or found the voltage it takes to make a liquid divid with electric pressure and I found that site. Still learning how to apply the equation but it seem Taylor had already done this before.

Just asking and answering questions I might have on the Meyer technology to further my knowelge on the subject.


h2opower.

Good reading H20power!!

[pmazz850]

Iīve finished Revision 0.2 of the Stan Meyer freedom circuit board.

The circuit has not been tested up yet, but I have corrected the detected errors of the very first version. Those high power circuit sections are realized with enhanced copper connection lines.

Iīll immediately give the layout to the manufacturer so that it will return back as a pcb in 10 days. Then Iīll add the circuits so that it boots up in lets say 15 days from now.
File sm2.pdf is a real sm2.zip (so please rename after download) and contains several files:
The named gerber-files are for the pcb manufacturer, sm1.sch is the KiCad scheme, sm2.net is the netlist and sm6_4.brd is the final board file.
freedom circuit rev. 0.2.pdf gives you a quick view at the board.

Iīll supply further informations to you as soon as I have assembled the board.
Please download now sm2.pdf and archive so that it`s spread …

greetings,
bussi04

Thanks for the update and for your work on the circuit. Its much needed for me!

[h20power]

Thanks Bussi04,

Now everyone has a base to work from on their expirements, one that controls the voltage amplitude so we can simply raise or lower the voltage as Meyer talks about.

Your welcome pmaz850, I thought I'd share some of my line of thinking with everyone since both of the two sites I just posted goes to further our understanding on how water can be used as a source of fuel by the water fuel injectors.

Energy independence is now within reach , we just have to build it


h2opower.

[Tecstatic]

Hi bussi,

Nice layout

But..

May I suggest you add a GND layer to the top layer.

At the engineering study I leaned this the hard way.

I made a pre-graduate project much the same type as you have just made with 40xx ICs.

It worked nicely at the laboratory table, it was a speed control for a pump.

It also worked well at the factory when I installed it in the weekend together with a technician.

Monday morning they called me, that the controller was unstable. It was unstable each time a big electric motor just on the other side of the wall started.

They needed the control to optimize the production, but after some thought I decided to take it down. After all this was just a study work, that made it too far. At that time I realized how important good EMC properties are to a circuit, and that I had too much to learn relative to the risk of destroying the expensive material being pumped.

I'm sorry, I have to do some criticism, but you risk frustrations, wasting money and loosing 15 days of progress.

Please read this document from my thread.

"This design note is nice for general tips when making PCB layouts:"

http://www.atmel.com/dyn/resources/p...ts/doc1619.pdf

And please note:

1. All ICs must have a decoupling capacitor between GND and VCC.

2. For the decoupling capacitors to work, you need the GND plane.

3. Check your GND and VCC net routing by using the "Net highlight" and clicking the nets.

4. Connect the "power GND" to the "signal GND" through one single short track, you do this by making two GND zones one for the signal part and one for the Power part connected by a single track. This avoids large currents in the signal area.
I once used this trick among others to reduce noise to get 18 bit of resolution, not that easy, try to compare 1% to 1 divided by 2^18.

5. I put a GND zone on the component layer of your layout, and because of the many tracks on the component layer, the GND plane is much fragmented. You can put some of the most fragmenting tracks manually to the solder side. You can also put a GND plane on the solder side and put vias to "stitch" the two planes together so they "help" each other reducing the area of the current loops from the ICs. This will greatly reduce the power rail noise, so your circuit can run with stability. Remember to put some vias at the edges for each 10mm.

6. Avoid signal tracks in the power area.

7. When you control a transistor through a base resistor, put the resistor close to the transistor, having the resistor signal end in the signal area, and the resistor base end in the power area.

8. You did not include the diagram, so I could not run a DRC on that. Use the button with magnifying glass and check mark ("Schematic Electric Rules Check").

9. I did check the PCB, you have two pairs of unconnected pads. (use the button "Pcb Design Rules Check").


Please don't feel blue because of my review.

Making PCBs well has a long learning curve. Despite the many things I commented, I must also say you have done a good job for your first PCB, some never learn to do it well. You can be proud you got this far in first attempt

But I suggest you give it some more effort. As it is right now, you will end up loosing your hair.

And this is normal to have "afterwork". When I finish a PCB, I usually have one more day of work to check with highlight each net for reasonable routing, that parts are not occupying the same 3D space etc.

If you know who is going to make the PCB, ask them for a document describing the rules and limitations for PCBs they make. This can also end up saving money and time.

Good luck with the next step

Eric

[bussi04]

Hi bussi,

Nice layout

But..

May I suggest you add a GND layer to the top layer.

At the engineering study I leaned this the hard way.

I made a pre-graduate project much the same type as you have just made with 40xx ICs.

It worked nicely at the laboratory table, it was a speed control for a pump.

It also worked well at the factory when I installed it in the weekend together with a technician.

Monday morning they called me, that the controller was unstable. It was unstable each time a big electric motor just on the other side of the wall started.

They needed the control to optimize the production, but after some thought I decided to take it down. After all this was just a study work, that made it too far. At that time I realized how important good EMC properties are to a circuit, and that I had too much to learn relative to the risk of destroying the expensive material being pumped.

I'm sorry, I have to do some criticism, but you risk frustrations, wasting money and loosing 15 days of progress.

Please read this document from my thread.

"This design note is nice for general tips when making PCB layouts:"

http://www.atmel.com/dyn/resources/p...ts/doc1619.pdf

And please note:

1. All ICs must have a decoupling capacitor between GND and VCC.

2. For the decoupling capacitors to work, you need the GND plane.

3. Check your GND and VCC net routing by using the "Net highlight" and clicking the nets.

4. Connect the "power GND" to the "signal GND" through one single short track, you do this by making two GND zones one for the signal part and one for the Power part connected by a single track. This avoids large currents in the signal area.
I once used this trick among others to reduce noise to get 18 bit of resolution, not that easy, try to compare 1% to 1 divided by 2^18.

5. I put a GND zone on the component layer of your layout, and because of the many tracks on the component layer, the GND plane is much fragmented. You can put some of the most fragmenting tracks manually to the solder side. You can also put a GND plane on the solder side and put vias to "stitch" the two planes together so they "help" each other reducing the area of the current loops from the ICs. This will greatly reduce the power rail noise, so your circuit can run with stability. Remember to put some vias at the edges for each 10mm.

6. Avoid signal tracks in the power area.

7. When you control a transistor through a base resistor, put the resistor close to the transistor, having the resistor signal end in the signal area, and the resistor base end in the power area.

8. You did not include the diagram, so I could not run a DRC on that. Use the button with magnifying glass and check mark ("Schematic Electric Rules Check").

9. I did check the PCB, you have two pairs of unconnected pads. (use the button "Pcb Design Rules Check").


Please don't feel blue because of my review.

Making PCBs well has a long learning curve. Despite the many things I commented, I must also say you have done a good job for your first PCB, some never learn to do it well. You can be proud you got this far in first attempt

But I suggest you give it some more effort. As it is right now, you will end up loosing your hair.

And this is normal to have "afterwork". When I finish a PCB, I usually have one more day of work to check with highlight each net for reasonable routing, that parts are not occupying the same 3D space etc.

If you know who is going to make the PCB, ask them for a document describing the rules and limitations for PCBs they make. This can also end up saving money and time.

Good luck with the next step

Eric

Hi Eric,

thanks for your valuable review. Iīll take those tips up and update the board layout integrating the EMC aspects.
I think it takes some more days to do so and I think the next update will be next monday.

Actually I have added the layout scheme and the project file to the lib sm2.pdf at my recent link.

There are some questions raising towards your implementation tips:

I think I canīt make the board without using the autoplace and autoroute functions on a 100x160mm board.

But how can I then fix a Resistor position so that one part goes to the power area and the other end goes to the signal area? Itīs the same for the decoupling capacitances that must stay near the circuit. Can I group components and direct the autoplace function to obey the grouping directive? Can I autoplace/-route to a certain point, manual place/route and continue autoplace/-route?

In this layout there were only 2 pairs of not connected pads. Then I was lucky because the other runs of the autorouter often made 9 pairs of open pads or more for the same circuit.

maybe the solution is to expand the board size.


greetings,
bussi04

[Tecstatic]

General layout tips and tricks

Hi Eric,

thanks for your valuable review. Iīll take those tips up and update the board layout integrating the EMC aspects.
I think it takes some more days to do so and I think the next update will be next monday.

Before doing too much work, please get the document from the PCB factory.

Actually I have added the layout scheme and the project file to the lib sm2.pdf at my recent link.

May I suggest you use this directory layout:

develop/fe/sm_old/hw/

and put your project files there. Just one of each file, and no numbering.

Have

develop/fe/sm_old/hw/backup

to put your numbered backups. Use sub directories for each save I you like.

Then develop/fe/sm_old/hw/ contains your project files without version numbering. No old and obsolete files here.
Add a project log file with the most recent work on top,
Each entry holds date, bussi, and a short description of the work done.

When you publish your work use the 4th button in the project manager window "Archive all project files" to make your .zip file.

There are some questions raising towards your implementation tips:

I think I canīt make the board without using the autoplace and autoroute functions on a 100x160mm board.

I don't agree.

I think we have to focus on the objective that you want to create a prototype board with a fair chance to work as expected.

It is not about creating a piece of art. I guess it is a bit confusing though when I speak of good practice, and what is necessary. The GND plane is a must, and then the worst layout issues can be corrected to get a usable result. What we need is a stable supply grid with an acceptable noise level, and some routing that has no significant current loops in the 40xx signal area, and avoiding to much longer tracks than necessary. Then you are OK routing wise.

But how can I then fix a Resistor position so that one part goes to the power area and the other end goes to the signal area? Itīs the same for the decoupling capacitances that must stay near the circuit. Can I group components and direct the autoplace function to obey the grouping directive? Can I autoplace/-route to a certain point, manual place/route and continue autoplace/-route?

KiCad is also an "editor". Having a "completed " PCB, does not prevent you from moving a component by deleting the the connected tracks, moving the component and reroute the tracks. Everything works incrementally from where you are.

Try deleting the R39 pin 1 track. move R39 to sit below Q8, and do an "Autoroute pad" for both the R39 pads. No trouble, right ?

Try highlighting the net on SW5, pin 2. This track is a loop enclosing half of the PCB area although the pads to connect are quite close to each other. You can re-route that track much better yourself.

Having said that, the most important step is the placement. I do this manually for best result. I study the diagram to identify parts to group, and then how groups are positioned relative to each other. Then I start the placement of parts, and how they should be rotated to minimize the track length and avoid "cluttering" where some tracks makes it almost impossible to route the PCB. Use 3rd button to the right "Display local ratsnest (pad or module)".

As an exercise try moving all your components with local ratnests on. Use the zoom button to make the layout full screen. Place the cursor on a component, press the "m" key, move it a bit and abort the move with the ESC button.
This gives an excellent view on how good the placement is.

You don't need many tracks as the one mentioned above to make it hard for yourself.

When you add GND plane to both sides of the PCB, then with a reasonable amount of work you can have GND close to the ICs VCC pins. Do yourself a favor and buy a bunch of 100nF 1206 ceramic surface mount capacitors. They are so compact that you can probably add the caps without moving anything. And they are still so big that everyone can do the solder work. I use components down to the 0402 size ( 40 mills long, 20 mills wide).

May I add they also do a better job decoupling the ICs.

This got long again.

Remember what I said about layouts of old style logic boards versus the mainly "star" layout using a uC. I guess you have now seen in detail what my point is.

I have now given you most of the basic tips for making the PCB. But as I have mentioned, my interest is using the newer technology.

Let me say I have not reviewed the schematic, and not the PCB either. I have just pointed at some issues I spotted right on.

Please feel free to ask more specific questions, but for now I will focus on progress with my own solution.

In this layout there were only 2 pairs of not connected pads. Then I was lucky because the other runs of the autorouter often made 9 pairs of open pads or more for the same circuit.

maybe the solution is to expand the board size.

greetings,
bussi04

You still have "black" areas, so you have the space you need. One tip more. Generally don't put components too close to the edge, it is more easy to route then.

Eric

[bussi04]

freedom circuit available for experimental work

Here we are!

Rev. 0.3 of the beta pcb for the Stanley Meyer freedom circuit is available. Tecstaticīs annotations are integrated in this Rev.

Download sm3.pdf, rename it to sm3.zip, expand it into the KiCad project directory, move bulib.lib to $KiCadRoot\share\library, move bulib.mod to $KiCadRoot\share\modules and you are ready to go with the pcb scheme using KiCad.

Those 2 JPGs show the virtual board layout. There are only 4 manual bridges to be done – have a look to the arrows at sm3.jpg.

For pcb manufacturing you need the 8 gerber files from the zip: those 7 ending with .pho and 1 sm3.drl.

Iīll put them to the manufacturer and Iīll get back a pcb after 2 weeks.

Now letīs enter next experimentation level and put all parts together.

greetings,
bussi04

[Tecstatic]

Hi Bussi,

This is much better

However I stumbled upon an important thing.

A 40xx gate is in reality a high gain amplifier, so unused inputs must be tied to VCC or GND, your choice.

This avoids IC increased consumption, heating and reducing noise (gate does not oscillate).

Luckily this is easy to do.

And while you have the file open, it is a good idea to "stich" some of the GND plane fragments together with vias.

And maybe move the U1 to the signal side, as it is the reference for the logic circuits, so no need to introduce switching noise to the logic supply.

I assume the power part will have some high voltages, so maybe 80mils zone clearance on the power part would be better.

Now the most apparent problems are weeded away, so it can hopefully be functional.

Sorry for my "eternal" corrections, I may seem critical, but not a as "critical" as the mounted circuit, if it has flaws.

But look at your layout, you have taken a giant step from the previous layout

Eric

[Tecstatic]

The "stitch" vias has no connections

Hi Bussi,

Dare I post more on this subject, but maybe I was wrong not to tell how to do the changes.

For the "stitch" vias, locate a GND pad nearby, place a track from there to the location for the via, and change layer, then the via is connected to the GND net, so you get it connected.

-----

For changing the zone clearance:

Set the "Add zones" button on.

Right click the hatched edge of the zone border and select a zone.

On the next menu select Zones->Edit Zone Params

Set the "Zone clearance value" as needed and click OK.

To refill the zone:

Right click the hatched edge of the zone border and select a zone.

On the next menu select Zones->Fill zone.

@everyone,

Please excuse me if some of my "help" is redundant to you, as I also consider this can be educational for newcomers to KiCad.

If another member installs KiCad and your posted sm circuit, then the file is nice for practicing. If something is messed up start with a new copy of the original circuit. Try practicing, and you will quickly learn some of the basics, enabling you to do your own PCBs.

Eric

[bussi04]

freedom circuit rev 0.5 uploaded - attention: major changes necessary

There are no changes in the circuit scheme. I integrated functional vias and adopted the clearance parameter to 0.8 according to tecstatics annotations. To look at the scheme you have to use KiCad. So there is a simple installation instruction for MS$ at http://www.energeticforum.com/78410-post107.html.

greetings,
bussi04

------------------------------------------------------------------------
unfortunately I have detected errors in rev. 0.5. sorry for any inconvenience. there are workarounds and later Iīll make a general correction rev. but before the circuit must be functionally tested in detail and improved by several testers. testers please send a PM to bussi04.

error list:
---------
01/03/10 E01:U9 74LS93 has a wrong layout due to an old datasheet pin description - solved, workaround available, if needed please PM bussi04
01/03/10 E02: U1 7805 has wrong layout - solved, U1 must be soldered connecting pin1 of pcb to pin3 of U1, pin2 pcb to pin2 of U1, pin3 pcb to pin1 of U1
01/03/10 E03: Q1 transistor has wrong layout - solved, Q1 must be soldered connecting emitter of Q1 to collector of pcb, collector of Q1 to emitter of pcb, base of Q1 to base of pcb
01/03/10 E04: Q2 transistor has wrong layout - solved, same as E03
01/03/10 E05: Q9 transistor has wrong layout - solved, same as E03
01/06/10 E06: transistor queue of SM Fig. 5 doesnīt fit the needs (Q3 to Q5) - solved, workaround available
01/12/10 E07: analog switch U6 CD4066 is not connected to GND - solved, make a bridge from pin 6 of U6 to pin 7 of U6
01/12/10 E08: analog switch U6 CD4066 is connected to +12V - solved, connect pin 14 of U6 to +5V by interrupting connection between pin 14 of U6 and pin 14 of pcb and then bend pin 14 of U6 and connect it to +5V


01/30/10 attention:
-------------------
now that the circuit is built and tested there are major changes necessary to make it run. itīs possible but not easy to use the pcb layout 0.5 and add another pcb with the circuit workarounds. there will be another rev 0.6 describing the corrected circuit scheme.